The present invention relates in general to random access memories and in particular to a circuit for sequentially selecting memory cell columns in a random access memory.
A typical random access memory (RAM) includes an array of rows and columns of memory cells, each cell storing a data bit. During either a memory read or write cycle, input data conveying row and column addresses identify the row and column of the particular memory cell with respect to which it is desired to read out or store a data bit. Each column of memory cells uses a pair of "bit lines" to convey a data bit between cells of the column and the data input and output circuits. Gates driven by a row address decoder connect only one cell in each column to the column bit lines, and gates controlled by a column address decoder connect only the bit lines of one column to the data input and output circuits. Thus, during a read or write cycle, bit lines couple only the single memory cell residing in the addressed row and column to an output or input circuit and only that single memory cell transmits or receives a data bit.
To limit the size of a bus accessing the memory, row and column addresses are usually sent to the memory sequentially over the same address lines. The row address may be placed on the address bus first and then latched onto the row address decoder input terminals in response to an input row address strobe signal. The column address is then placed on the address bus and applied to the column select circuit input terminals in response to an input column address strobe signal.
In many applications, data bits stored in cells along one row are read or written sequentially. For example, a video display may be organized into an array of pixels, and pixel data stored in successive memory cells along each row of a video RAM may control color of successive pixels in a corresponding row of the display. To refresh a display, the data bits stored in cells along each memory array row are read out to a video driver in serial fashion. To speed up memory addressing when sequentially accessing memory cells along a row, the processor or other device accessing the memory provides the row address only once to the memory to select the row being accessed, and then sends a sequence of column addresses to the memory without changing the row address. By progressively incrementing the column address, cells along the selected row are selected sequentially for read or write access.
Typically, a processor or other device loads a starting column address into a programmable counter. Thereafter, during each memory access cycle, the counter increments and transmits the column address to the column address decoder. This system eliminates the need to send new row and column addresses to the memory during each memory access cycle; however, the time required to load and activate the counter adds to total memory access time, and the large number of gates required to implement the circuitry can require significant amounts of chip space and power.